Design Engineer

Summary

Posted: Oct 9, 2024

Role Number:200572626

The Apple IP design team is looking for an experienced engineer to develop multiple IPs for Apple SoCs (in Storage, Computer Vision and RISC-V CPU domains). In this Role you will get to handle micro-architecture definitions, RTL coding, block level simulations and synthesis.
Role expectations include working with partner design teams, physical design, verification, platform architecture and software teams to define the IPs micro architecture, implement the required HW and integrate it into multiple sub-systems in Apple SoCs. In addition, you will synthesize the digital design to the latest process nodes and participate in the implementation process. If you are looking for a challenging technical role with a broad system view in a complex, control-oriented IPs, this could be a great opportunity for you.
The role is relevant for all Apple sites: HRZ, Haifa, JRZ

Description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products very quickly. Do you want to bring passion and dedication to your job? There’s no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — strengthening our dedication to leave the world better than we found it. Do you want to join us to help deliver the next groundbreaking Apple products?

Minimum Qualifications

• 3+ year experience in VLSI design of Processor Cores/SoC.
• Familiar with advanced design practices (Clock/Voltage domain crossing and Low Power Design).
• Strong Verilog/System Verilog skills
• Familiar with CPU/ARM instruction set standard – an advantage
• Familiar with the various backend tools (synthesis and STA) – an advantage.
• Experience with scripting and programming experience using several of the following: Perl, C, Python, and TCL.
• BS.c/ MS.c in EE/ CE

Preferred Qualifications

• Familiar with verification methodologies – an advantage
• Familiar with CPU/ARM instruction set standard – an advantage
• Familiar with the various backend tools (synthesis and STA) – an advantage