Sr. Staff Engineer, DV Methodology Lead

Job Description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.

We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re building the next generation of AI-optimized CPUs, and we need a verification leader with deep experience navigating complex design validation at scale. As Design Verification Lead, you’ll own the verification strategy for our RISC-V CPU architecture—the technical backbone ensuring our designs meet functional and performance requirements through manufacturing.

You’ll partner with our architecture and design teams to develop a comprehensive verification roadmap that identifies and addresses critical design issues early in the cycle, mentor a growing team of verification engineers, and establish the automation infrastructure necessary to maintain iteration velocity. This leadership role requires someone with substantial hands-on experience in large-scale CPU verification who understands both the strategic and tactical dimensions of design validation.

This is a hybrid role is in Austin, TX or Santa Clara, CA, with remote possibilities based on qualifications. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You AreYou have led testbench development and architectural decisions for complex verification projects. You understand the tradeoffs in testbench structure and have applied that knowledge across multiple significant designs. You have substantial hands-on experience with SystemVerilog and UVM.

You can design verification architectures from first principles and are comfortable optimizing implementations without external references. You recognize infrastructure and automation as critical components of verification effectiveness.

You have either built or directly contributed to CAD tools and verification infrastructure that meaningfully improved team productivity. You operate effectively across both strategic planning and implementation. You can engage in architectural discussions with design leadership and independently debug complex verification issues.

What We Need 8+ years of experience in CPU or complex SoC verification. Demonstrated experience closing coverage on designs of comparable complexity and working through silicon-scale debug cycles. Expert-level proficiency in SystemVerilog and UVM.

Ability to architect, implement, and optimize testbenches independently. Strong scripting skills, particularly Python. Experience building internal tools and automation that enhances team workflows and integrates verification infrastructure.

C experience is a plus. Relevant for simulator development or low-level debug work, but not required if your verification automation practice is well-established. What You Will Do and MentorVerification strategy aligned with silicon outcomes.

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