Technical Leader – Dataplane Engineering Available in 51 locations Available in 51 locations

Job Description

Meet the Team Join the core Hypershield Data Plane team within Cisco’s Security Business Group—an industry-first effort redefining how modern distributed security is built. We are engineering the data path for a highly available, AI-designed security fabric that protects applications across public clouds, private data centers, and physical environments. This team is building segmented firewalling directly in the data plane—a first-of-its-kind innovation not available elsewhere in the industry.

Engineers on this team get end-to-end ownership of packet processing systems, deep exposure to DPUs (AMD), NPUs, and P4, and the opportunity to shape foundational architecture in a fast-paced, high-visibility environment. If you want to work on the core of the data path, build something new, and learn deeply from day one—this is the place. Your Impact In this role, you will design, build, and optimize the data plane for Cisco Hypershield using C++, P4, and hardware offload technologies such as DPUs and NPUs. You’ll work hands-on with AMD DPU specifications, packet processing pipelines, and performance-critical components from day one.

Success in this role means operating in a fast-paced model—quickly absorbing the architecture, contributing to data-plane development immediately, and delivering reliable, high-performance code with minimal hand-holding. You will: Design and implement data-plane features using P4, microcode, and C++ across DPU/NPU architectures.

Bring up hardware platforms, integrate SDKs, and debug low-level packet-processing behavior. Work from AMD technical specifications to define and build performant pipelines. Collaborate closely with internal teams (control plane, management plane, platform) to deliver end-to-end datapath functionality.

Drive system-level architecture discussions and influence design choices for high-throughput and low-latency packet processing. Minimum Qualifications Bachelor’s degree in Computer Science, Electrical Engineering, or related field. 7+ years of experience in packet processing (e.

g. , DPDK, TCP reassembly, high-throughput pipelines).

Programming experience in C/C++ and experience with P4 or microcode/U-code development. Experience bringing up platforms or ASICs in Linux-based environments. Hands-on experience building or leveraging hardware acceleration with DPUs or NPUs.

Preferred Qualifications Experience working with AMD DPUs, Broadcom, Marvell, or Intel data-path hardware. Deep understanding of P4 compiler behavior, pipeline stages, and programmable switch architecture. Experience with performance analysis, tuning, and optimization of high-throughput systems.

Prior background in designing test harnesses, working with third-party SDKs, or hardware debug. Experience owning features end-to-end in a distributed or high-availability networking product. Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

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